Extension makefiles

Extension makefiles can be used where certain build steps are required that are not catered for by the generated makefiles. Extension makefiles are makefiles to be run by make.exe (the GCC make utility) or nmake.exe (the Microsoft make utility). They must contain certain make targets. During build activities, abld will call the target corresponding to the build activity that is being carried out. This will then execute whatever commands your makefile specifies for that target.

The following table lists the required make targets:

All targets must be provided in an extension makefile. This should be done even if no commands are listed with a particular target, for the following two reasons:

• The target will be called, during the build, whether commands are listed or not

• nmake.exe/make.exe will generate an error if the target cannot be found.

An example of a simple extension makefile is given below:

MAKMAKE :
       echo this is an example

FINAL FREEZE LIB CLEANLIB RESOURCE RELEASABLES CLEAN BLD SAVESPACE :

This prints this is an example to the console at the makefile construction stage of an abld, and does nothing for the other targets.

Note that:

• You can put multiple targets on the same line, as above.

• You must have a space or a tab at the start of lines containing target commands.

• Commands listed with each target can be calls to any tools or system commands that are available at build-time.

If different commands are required for the same target for different platforms, special nmake.exe/make.exe syntax can be used in conjunction with the $(PLATFORM) and $(CFG) macros that abld defines to carry out the different commands.

$(CFG) is defined as UDEB or UREL. $(PLATFORM) is WINS, ARMI, etc.

For example, the following nmake makefile prints ARMI MAKEMAKE COMMAND at the makefile stage for the ARMI target, or NOT ARMI BUILD for any other platform:

!IF "$(PLATFORM)" == "ARMI"
MAKMAKE:
    echo ARMI MAKEMAKE COMMAND
!ELSE
MAKMAKE:
    echo NOT ARMI BUILD
!ENDIF
    
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